Starting to Mix C and Verilog

Okay, time to stop. Starting to mix C and Verilog. 🤡 always @ (posedge INPUT_CLK) begin if(INPUT_VLE == 1) begin frame_bright_counter <= 0; end else { end

A social media post shows someone jokingly mixing C syntax with Verilog hardware-description code, using curly braces where Verilog expects a block structure. The clown emoji emphasizes the foolishness of continuing after recognizing the mistake, making it a reaction to confusing programming languages or writing invalid code. EN: A social media post shows someone jokingly mixing C syntax with Verilog hardware-description code, using curly braces where Verilog expects a block structure. The clown emoji emphasizes the foolishness of continuing after recognizing the mistake, making it a reaction to confusing programming languages or writing invalid code.

• @gentoomemes / 5882 2023-08-20