Pure Assembler vs SystemVerilog

me: I write pure Assembler, yeah! start: bsr STATUS,RP0 movlw .00 movwf TRISB bct STATUS,RP0 led: movlw 170 SystemVerilog module alu(input logic [31:0] a, b, input logic [1:0] ALUControl, output logic [31:0] Result, output logic [3:0] ALUFlags); reg [32:0] Carry; always_comb begin case (ALUControl) 2'b00: Result, Carry = a + b; // overflow Flag // ALUFlags[0] = (~(a[31]^b[31]))^Result // Carry Out Flag // ALUFlags[1] = (Carry[32] == 1) > 1

A man laughing and drinking is shown behind screenshots of assembly code and SystemVerilog code. The joke is that someone claiming to write pure assembler is actually writing hardware-description language code, so the boast is misleading. It is used as a reaction to exaggerated technical claims or confusing one programming language with another.

• @profunctor_io / 5237 2020-09-01